1. Field of the Invention
The present invention relates to the backside metallization and dicing of microelectronic device wafers. In particular, the present invention relates to forming a substantially V-shaped notch extending into the microelectronic device wafer from a back surface thereof prior to metallization and dicing.
2. State of the Art
In the production of microelectronic devices, integrated circuitry is formed in and on semiconductor wafers, which is usually comprised primarily of silicon, although other materials such as gallium arsenide and indium phosphide may be used. As shown in FIG. 8, a single microelectronic device wafer 200 may contain a plurality of substantially identical integrated circuit areas 202, which are usually substantially rectangular and arranged in rows and columns. Two sets of mutually parallel sets of lines or xe2x80x9cscribe streetsxe2x80x9d 204 extend perpendicular to each other over substantially the entire surface of the microelectronic device wafer 200 between each discrete integrated circuit area 202.
After the integrated circuit areas 202 have been subjected to preliminary testing for functionality (wafer sort), the microelectronic device wafer 200 is diced (cut apart), so that each area of functioning integrated circuitry 202 becomes a microelectronic die that can be used to form a packaged microelectronic device. One exemplary microelectronic wafer dicing process uses a circular diamond-impregnated dicing saw, which travels down the scribe streets 204 lying between each of the rows and columns. Of course, the scribe streets 204 are sized to allow passage of a wafer saw blade between adjacent integrated circuit areas 202 without causing damage to the circuitry therein.
As shown in FIGS. 9 and 10, a microelectronic device wafer 200 may have guard rings 206 which substantially surround the integrated circuit areas 202. The guard rings 206 extend though an interconnection layer 208 (see FIG. 10). The interconnection layer 208 comprises layers 212 of metal traces separated by layers of dielectric material layers on a semiconductor wafer 214. The interconnection layer 208 provides routes for electrical communication between integrated circuit components within the integrated circuits. The guard ring 206 is generally formed layer by layer as each layer 212 is formed. The guard ring 206 assists in preventing external contamination encroaching into the integrated circuitry 202 between the layers 212. The microelectronic device wafer 200 also includes a backside metallization layer 216 on a back surface 218 of the semiconductor wafer 214, which will be subsequently discussed.
Prior to dicing, the microelectronic device wafer 200 is mounted onto a sticky, flexible tape 222 (shown in FIG. 10) that is attached to a ridge frame (not shown). The tape 222 continues to hold the microelectronic die after the dicing operation and during transport to the next assembly step. As shown in FIGS. 11 and 12, a saw cuts a channel 220 in the scribe street 204 through the interconnection layer 208, the semiconductor wafer 214, and the backside metallization layer 216. During dicing, the saw generally cuts into the tape 222 to up to about one-third of its thickness. The dicing of the wafer forms individual microelectronic dice 224.
As shown in FIG. 13, a microelectronic die 224 is attached to a substrate 226, such as a motherboard, by a plurality of solder balls 228 extending between interconnection layer 208 and the substrate 226. A heat dissipation device 232 is attached to the backside metallization layer 216 by a thermal interface material 234. The thermal interface material 234 is usually a solder material including, but not limited to, lead, tin, indium, silver, copper, and alloys thereof. However, it is well known that most solders do not wet (i.e., stick to) semiconductor wafers 214 (particularly silicon-based semiconductor wafers). Thus, the backside metallization layer 216 is selected to adhere to the semiconductor wafer back surface 218 and wet with the thermal interface material 234. The backside metallization layer 216 is usually a metal material including, but not limited to, gold, silver, nickel, and the like.
However, in the dicing of microelectronic device wafers 200, dicing saws (metal impregnated with diamond) may cause chipping of the backside metallization layer 216 to expose a portion of the semiconductor wafer back surface 218. Since the thermal interface material 234 does not wet the semiconductor wafer back surface 218, microgaps 236 form between the thermal interface material 234 and the semiconductor wafer back surface 218, and a poor (sagging) thermal interface material fillet 238 results between the heat dissipation device 232 and the backside metallization layer 216, as shown in FIG. 14.
During the operation of the microelectronic die 224 stresses occur at the interface between the backside metallization layer 216 and the thermal interface material 234, particularly at comers/edges 244 of the microelectronic die 224. These stresses can result in delamination, generally starting at the microelectronic die comers/edges 242. This delamination results in a decrease in thermal conductivity and moisture encroachment. With a decrease in thermal conductivity comes the risk of overheating in the microelectronic die 224, which can result in the damage or destruction thereof. The microgaps 236 and the poor thermal interface material fillet 238 exacerbate the delamination.
Therefore, it would be advantageous to develop techniques to effectively dice microelectronic device wafers while reducing or substantially eliminating the possibility of delamination propagation.